The transition from synthesis to hardware is not always smooth. A number of designs had issues around clocking and power that only manifest on the real hardware.
Incorporate an MMCM
We recommend incorporating an MMCM (clock generator) into your design to ensure hitting the target clock frequency. For examples see some of the submissions from round 1 (including the entry from Eric Pearson) or https://github.com/supranational/vdf-fpga/blob/pll_cdc/msu/rtl/msu_cdc.sv . Some designs don’t run at the target frequency on F1 without this level of control.
Precompuation related to the modulus or the exponent does not need to be inside the timer.
Use the test portal to ensure repeatability
We need to be able to fully reproduce your results from scratch. The test portal is a good way to make sure your build results are consistently repeatable from source files.
Visualizing test portal and SDAccel results
SDAccel and the test portal produce intermediated .dcp files which are checkpoints of the design. You can open these with Vivado (vivado my_file.dcp) to view your design, run reports, etc.
Vivado Project and On-premise Correlation
Be wary of trusting Vivado in project mode as fine tuning gets into picoseconds. We’ve also seen subtle differences between an on-premise environment and the AWS AMI. Test periodically in AWS to avoid surprises.