1 Verifiable Delay Function Evaluation ASIC
- 1.1 Introduction
- 1.2 Verifiable Delay Function
- 1.3 Requirements
- 1.4 ASIC Overview
- 1.5 Modular Squaring Unit
- 1.6 Input/Output Interface
- 1.7 Control Logic
  - 1.7.1 Command Format
  - 1.7.2 Commands
    - 1.7.2.1 Write Register
    - 1.7.2.2 Read Register
- 1.8 Clock
- 1.9 Thermal Protection
- 1.10 Reset
- 1.11 Debug
- 1.12 Registers
  - 1.12.1 MSU
  - 1.12.2 Control Logic
  - 1.12.3 Results Status and Control
  - 1.12.4 IO Logic
    - 1.12.4.1 IO Status and Control
    - 1.12.4.2 Clock
  - 1.12.5 Core Clock Divider
  - 1.12.6 Control Clock Divider
  - 1.12.7 Thermal
- 1.13 ASIC Identification
- 1.14 Pin List
- 1.15 System Level Operation

Verifiable Delay Function Evaluation ASIC

Introduction

The VDF ASIC is a fixed function device that takes a message hash, difficulty level, and interval then returns the VDF result at each interval. The intended usage is part of Ethereum 2.0’s transformation, a cornerstone in several of Filecoin’s core components, as well as other blockchains initiatives.

Verifiable Delay Function

The Verifiable Delay Function (VDF) used in the ASIC is based on the work of Benjamin Wesolowski: Efficient verifiable delay functions

The VDF result

is generated by the following formula with the input hash

and difficulty

:

Typically

will be on the order of 2⁴⁰.

The proof is calculated by:

For more information on VDF’s refer to the project research page: VDF Research

Requirements

Input Bandwidth	TODO – small - < 10KB per job depending on precomputed constants
Output Bandwidth	TODO – little bigger, still small - < 2Mbps
Power	TODO – depends on system ~10W?
Mod Square Latency	TODO – 2 ns?
Thermal	TODO – 0-100 C
IO Voltage	TODO – 0.8 V
Logic Voltage	TODO – 0.75 V
PLL Reference	TODO – 25 MHz

ASIC Overview

There are five main blocks in the VDF ASIC: Modular Squaring Unit, Input/Output Logic, Control Logic, PLL, and Thermal Sensor.

Modular Squaring Unit

The Modular Squaring Unit (MSU) is the primary compute engine in the VDF ASIC. The engine takes a 2048 bit input

and returns

where

is a predefined 2048 RSA modulus. There is a built-in feedback loop that continuously takes the output of the current result as the input to next. This is required for the iterative modular squaring of the VDF evaluation function.

The MSU has control logic around the compute engine to keep track of the current iteration and optionally return intermediate values for use in proof generation. Note the proof generation aspect of VDFs is not applicable in this ASIC.

Input/Output Interface

Given the small volume of data that goes in and out of the ASIC, I2C is used as the low speed I/O protocol. The benefits of I2C are being well known, robust, and very simple. Alternatively there are options to go with SPI, UART, or a non-standardized basic serial interface if necessary.

For details on I2C, please refer to the user guide from NXP.

The ASIC is configured as an I2C slave and is not required to be fully I2C protocol compliant. Given the ASIC will reside is a known environment with fixed micro-controller, interoperability in unknown systems is not required.

Note that preliminary thoughts on bandwidth requirements feeding intermediate values to the prover indicate I2C may not be not enough. In that case the inclination is to use SPI.

Control Logic

All control of the ASIC is done through a fixed state machine in the control logic.

Command Format

cmd/opcode
chip id
address/register
length
data
results
status
end of cmd/return
checksum

Write

3b	5b	8b	16b	variable
Opcode	Chip ID	Address	Length	Data

Read

3b	5b	8b
Opcode	Chip ID	Address

Evaluator ASIC Design

Verifiable Delay Function Evaluation ASIC

Introduction