FPGA Competition

Welcome to the home page of the VDF Alliance FPGA Competition.



Getting Started

To get started check out the baseline implementation at Github and the Getting Started Guide.


Prizes and Judging

In Round 1 the first place winner (the contestant with the lowest latency) will receive $3000 for each nanosecond improvement from the Round 1 baseline which is set at 50ns.

You can read more about how the competition will be judged at the Contest Judging page. The parameters used for judging can be found at the Contest Problem Parameters page.


Discussion

For general discussion about the competition please join the Telegram Channel or Discourse page.


Contest Information and Help

Please read the Official Competition Rules. If you'd like to compete please fill out the Entry Form.

Please direct entry submissions and any questions to hello@vdfalliance.org.


Timeline

Round 1: From August 1, 2019 to September 30, 2019

Round 2: From approximately October 15, 2019 to December 30, 2019.