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- Estimate performance for all qualifying designs using the SDAccel synthesis clock freq and simulation cycles/sq. For example, given 8 cycles/sq and 161Mhz, total latency is (1/161)*1000*8 = 49.7ns.
- Select the design with the highest estimated performance as well as any designs within 3ns of that result.
- Execute these designs on AWS F1. Measure performance and functional correctness of 1B repeated squarings. Contestants should be aware that only certain clock frequencies available natively from AWS F1, as documented in: https://github.com/aws/aws-fpga/blob/master/hdk/docs/dynamic_clock_config.md. Designs may use an MMCM or clock generator to operate at alternate frequencies.
- The winner will be the design with the lowest latency per squaring over 1B iterations as measured by the RTL kernel driver (https://github.com/supranational/vdf-fpga/blob/rc1/msu/sw/main.cpp). The expected command line is:
host -i 1 -f 1073741824 -n 1024 -s 0x<random input to be revealed>