FPGA Competition
Welcome to the home page of the VDF Alliance FPGA Competition.
Getting Started
To get started check out the baseline implementation at Github and the Getting Started Guide.
Prizes and Judging
In Round 1 the first place winner (the contestant with the lowest latency) will receive $3000 for each nanosecond improvement from the Round 1 baseline which is set at 50ns.
You can read more about how the competition will be judged at the Contest Judging page. The parameters used for judging can be found at the Contest Problem Parameters page.
Discussion
For general discussion about the competition please join the Telegram Channel or Discourse page.
Contest Information and Help
Please read the Official Competition Rules. If you'd like to compete please fill out the Entry Form.
Please direct entry submissions and any questions to hello@vdfalliance.org.
Timeline
Round 1: From August 1, 2019 to September 30, 2019
Round 2: From approximately October 15, 2019 to December 30, 2019.
Comments
If the prize pool is exhausted in the first round we would likely evaluate adding additional funds to the prize pool and continuing with the second round of the competition.
so what did you guys decide with this?
with the new baseline of 28.6ns, is the second round prize of $5k per ns of improvement in force for new solutions bringing the run time down to 8.6ns?
Can someone apply directly during the second round, or you have to apply for the first round to get considered for the second?
You can apply directly during the second round.
when will the results from the first round be posted? how many entries were there?
if, say, sometime during the first round, somebody happens to come up with an entry solution that meets the criteria and returns correct answers in a total time that implies a per iteration rate of >33ns better than the 50 (or is it 48?) nanosecond benchmark, would the second round then be canceled? i ask because in that case the $100k prize pool would then already be exhausted...
ok, thanks much!!