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In order to better reason about the potential performance of a hardware accelerated VDF, the Ethereum Foundation, Protocol Labs, the Interchain Foundation, and Supranational have collaborated to develop novel algorithms and semiconductor designs for VDFs. In the first phase of the engagement these collaborators partnered with Erdinc Ozturk of Sabanci University to develop a low latency VDF algorithm targeted at an ASIC architecture. The team was able to leverage this design to develop an FPGA implementation that solved a twenty-year-outstanding timelock puzzle at MIT that was developed by famed cryptographer Ron Rivest. While this design was focused on the evaluation component of VDFs, that is computing the sequential work required of a VDF, there is still a considerable amount of research to be completed to develop an efficient hardware accelerator to verify these functions. For example, the Rivest time lock puzzle took almost two months of computation to solve, and a similar amount of computational time to verify.
The goal of this proposal is to develop an ASIC hardware accelerator that can both evaluate the VDF function and quickly generate ‘proofs’. These proofs provide the ‘verifiable’ component of verifiable delay functions. Without an efficient means to generate proofs for VDFs, specialized hardware a large amount of parallel computing would be required by all nodes in the blockchain network to verify the correctness after the evaluation of the VDF calculations. By developing an accelerator that can both evaluate VDFs and generate proofs of their completion, VDFs can be leveraged to add randomness to decentralized consensus protocols in a trustless manner. By reducing the computational complexity of verifying VDFs, commodity hardware can be used by participants to maintain the state of a blockchain network.
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